%0 Journal Article
%A 柴苗苗
%A 邓军勇
%A 杜卓林
%A 谢晓燕
%A 杨坤
%A 尹芍润
%T Hardware-friendly Cycle-GAN and reconfigurable design
%D 2023
%R 10.19682/j.cnki.1005-8885.2023.2012
%J 中国邮电高校学报（英文）
%P 10-20
%V 30
%N 4
%X As a kind of generative adversarial network (GAN), Cycle-GAN shows an apparent superiority in image style
translation. The more complicated architectures with large number of parameters and huge computational
complexities, cause a big challenge in deployment on resource-constrained platform. To make full use of the
parallelism of hardware under guaranteed image quality, this paper improves the generator network to a hardware-friendly Inception module. The optimized framework is named simplified Cycle-GAN (S-CycleGAN), with greatly
reduced parameters of convolution, while avoiding the degradation of image quality from structural compression.
Testing with the apple2organge and horse2zebra datasets, the experiment results show that the images generated by
S-CycleGAN outperform the baseline and other models. The number of parameters reduces by 19.54%, memory usage cuts down by 9.11%, theoretical amount of multiply-adds (Madds) decreases by 17.96%, and floating-point operations per second (FLOPS) diminishes by 18.91%. Finally, the S-CycleGAN was mapped on the
dynamic programmable reconfigurable array processor ( DPRAP ), which calculate the convolution and
deconvolution in a unified architecture, and support flexible runtime switching. The prototype systems are
implemented on Xilinx field programmable gate array (FPGA) XC6 VLX550 T-FF1759. The synthesized results
show that, with 150 MHz, the hardware resource consumption is reduced by 52% compared to the recent FPGA
scheme.
%U https://jcupt.bupt.edu.cn/CN/10.19682/j.cnki.1005-8885.2023.2012