%0 Journal Article
%A CHANG Li-Bo
%A DU Hui-Min
%A HU Yi-Jing
%A YU Ji-He
%T <span>Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning</span>
%D 2024
%R 10.19682/j.cnki.1005-8885.2024.0005
%J Journal of China Universities of Posts and Telecommunications
%P 72-84
%V 31
%N 2
%X <div style="text-align:justify;">
	To apply a&nbsp;quasi-cyclic low density parity check (QC-LDPC) to different scenarios, a data-driven pipelined macro-instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm. The data-level parallelism is improved by instructions to dynamically configuring the multi-core computing units. Simultaneously, an intelligent adjustment strategy based on programmable wake-up controller (WuC) is designed so that the computing mode, operating voltage, and frequency of the QC-LDPC algorithm can be adjusted. This adjustment can improve the computing efficiency of the processor. The QC-LDPC decoders are verified on the Xilinx ZCU102 Field Programmable Gate Array (FPGA) board and the computing efficiency is measured. The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency. The maximum efficiency can reach up to 12.18 Mbit(s·mW)<sup>-1</sup>, which is more flexible than existing state-of-the-art processor for QC-LDPC.
</div>
%U https://jcupt.bupt.edu.cn/EN/10.19682/j.cnki.1005-8885.2024.0005